AUIRS2336S【PDF 29/37 页】IC GATE DRIVER HV 3PHASE 28SOIC

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AUIRS2336S

Routing and Placement : Power stage PCB parasitic elements can contribute to large negative voltage transients at

the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions,

it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side

emitter to negative bus rail stray inductance. However, where negative V S spikes remain excessive, further steps

may be taken to reduce the spike. This includes placing a resistor (5 ? or less) between the V S pin and the switch

node (see Figure 36), and in some cases using a clamping diode between V SS and V S (see Figure 37). See DT04-4

at www.irf.com for more detailed information.

Figure 36: V S resistor

Figure 37: V S clamping diode

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com ; use the Site Search

function and the document number to quickly locate them. Below is a short list of some of these documents.

DT97-3: Managing Transients in Control IC Driven Power Stages

AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04-4: Using Monolithic High Voltage Gate Drivers

AN-978: HV Floating MOS-Gate Driver ICs

www.irf.com

29

? 2009 International Rectifier

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